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HT67F5652 bảng dữ liệu(PDF) 122 Page - Holtek Semiconductor Inc |
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HT67F5652 bảng dữ liệu(HTML) 122 Page - Holtek Semiconductor Inc |
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122 / 224 page ![]() Rev. 1.00 1�� De�e��e� 0�� �01� Rev. 1.00 1�3 De�e��e� 0�� �01� HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU Programmable Gain Amplifier – PGA Therearethreeregistersrelatedtotheprogrammablegaincontrol,PGAC0,PGAC1andPGACS. ThePGAC0resisterisusedtoselectthePGAgain,ADCgainandtheADCreferencegain.As well,thePGAC1registerisusedtodefinetheinputconnectionanddifferentialinputoffsetvoltage adjustmentcontrol.Inaddition,ThePGACSregisterisusedtoselecttheinputendsforthePGA. Therefore,theinputchannelshavetobedeterminedbytheCHSP2~CHSP0andCHSN2~CHSN0 bitstodeterminewhichanalogchannelinputpins,temperaturedetectorinputsorinternalpower supplyareactuallyconnectedtotheinternaldifferentialA/Dconverter. • PGAC0 Register Bit 7 6 5 4 3 2 1 0 Na�e — VGS1 VGS0 AGS1 AGS0 PGS� PGS1 PGS0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit7 Unimplemented,readas"0" Bit6~5 VGS1~VGS0:REFP/REFNdifferentialreferencevoltagegainselection 00:VREFGN=1 01:VREFGN=1/2 10:VREFGN=1/4 11:Reserved Bit4~3 AGS1~AGS0:A/DconverterPGAOP/PGAONdifferentialinputsignalgainselection 00:ADGN=1 01:ADGN=2 10:ADGN=4 11:ADGN=8 Bit2~0 PGS2~PGS0:DI+/DI-differentialchannelinputgainselection 000:PGAGN=1 001:PGAGN=2 010:PGAGN=4 011:PGAGN=8 100:PGAGN=16 101:PGAGN=32 110:PGAGN=64 111:PGAGN=128 • PGAC1 Register Bit 7 6 5 4 3 2 1 0 Na�e — INIS INX1 INX0 DCSET� DCSET1 DCSET0 — R/W — R/W R/W R/W R/W R/W R/W — POR — 0 0 0 0 0 0 — Bit7 Unimplemented,readas"0" Bit6 INIS:Selectedinputends,IN1andIN2internalconnectioncontrolbit 0:Notconnected 1:Connected Bit5~4 INX1~INX0:Selectedinputends,IN1/IN2andthePGAdifferentialinputends,DI+/DI- connectioncontrolbits IN� IN1 DI+ DI- IN� IN1 DI+ DI- IN� IN1 DI+ DI- IN� IN1 DI+ DI- INX[1�0]=00 INX[1�0]=01 INX[1�0]=10 INX[1�0]=11 |
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