LAN9220 datasheet(119/142 Pages) MICROCHIP

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DS00002417A-page 119

LAN9220

6.5

RX Data FIFO Direct PIO Reads

In this mode the upper address inputs are not decoded, and any read of the LAN9220 will read the RX Data FIFO. This

mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the

FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address

when accessing the LAN9220. Timing is identical to a PIO read, and the FIFO_SEL signal has the same timing charac-

teristics as the address lines.

Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.

Note 6-4

When VDDVARIO is 3.3V or 2.5V, the maximum Tdoff time is 7ns. When VDDVARIO is 1.8V, the

maximum Tdoff time is 9ns.

FIGURE 6-4:

RX DATA FIFO DIRECT PIO READ CYCLE TIMING

Note:

The “Data Bus” width is 16 bits.

TABLE 6-5:

RX DATA FIFO DIRECT PIO READ TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcycle

Read Cycle Time

165

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time (see Note below)

133

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

Note 6-4

tdoh

Data Output Hold Time

Note:

An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends

when either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.

Parameters tcsh and tcsl must be extended using wait states to meet the tcycle minimum.

Data Bus

nCS, nRD

FIFO_SEL

A[2:1]

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