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LAN9220 bảng dữ liệu(PDF) 118 Page - Microchip Technology

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Giải thích chi tiết về linh kiện  16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
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LAN9220
DS00002417A-page 118
 2006-2017 Microchip Technology Inc.
6.4
PIO Burst Reads
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO Burst Reads can be
performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between
bursts for the period specified.
Note 6-3
When VDDVARIO is 3.3V or 2.5V, the maximum Tdoff time is 7ns. When VDDVARIO is 1.8V, the
maximum Tdoff time is 9ns.
FIGURE 6-3:
PIO BURST READ CYCLE TIMING
Note:
The “Data Bus” width is 16 bits.
TABLE 6-4:
PIO BURST READ TIMING
Symbol
Description
MIN
TYP
MAX
units
tcsh
nCS, nRD Deassertion Time
13
ns
tcsdv
nCS, nRD Valid to Data Valid
30
ns
tacyc
Address Cycle Time
165
tasu
Address Setup to nCS, nRD valid
0
ns
tadv
Address Stable to Data Valid
40
tah
Address Hold Time
0
ns
tdon
Data Buffer Turn On Time
0
ns
tdoff
Data Buffer Turn Off Time
Note 6-3
ns
tdoh
Data Output Hold Time
0
ns
Note:
A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both
nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Data Bus
nCS, nRD
A[7:5]
A[4:1]



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