LAN9220 datasheet(23/142 Pages) MICROCHIP

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DS00002417A-page 23

LAN9220

The RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN protocol identifier

for the third tag is treated as an Ethernet type field. The checksum calculation will begin immediately after the type field.

The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame it calculates the 16-bit

checksum. The RXCOE passes the Ethernet frame to the RX Data FIFO with the checksum appended to the end of the

frame. The RXCOE inserts the checksum immediately after the last byte of the Ethernet frame. The packet length field

in the RX status word (refer to Section 3.13.3) will indicate that the frame size has increased by two bytes to accommo-

date the checksum.

Setting the RXCOE_EN bit in the COE_CR—Checksum Offload Engine Control Register enables the RXCOE, while

the RXCOE_MODE bit selects the operating mode. When the RXCOE is disabled, the received data is simply passed

through the RXCOE unmodified.

FIGURE 3-6:

ETHERNET FRAME WITH VLAN TAG AND SNAP HEADER

FIGURE 3-7:

ETHERNET FRAME WITH MULTIPLE VLAN TAGS AND SNAP HEADER

Note:

• Software applications must stop the receiver and flush the RX data path before changing the state of the

RXCOE_EN or RXCOE_MODE bits.

• When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the MAC_CR—MAC

Control Register) and vice versa. These functions cannot be enabled simultaneously.

DST

SRC

L3 Packet

{DSAP, SSAP, CTRL,

OUI[23:16]}

{OUI[15:0], PID[15:0]}

Calculate Checksum

1DWORD

DST