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LAN9220 bảng dữ liệu(PDF) 31 Page - Microchip Technology

tên linh kiện LAN9220
Giải thích chi tiết về linh kiện  16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
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LAN9220 bảng dữ liệu(HTML) 31 Page - Microchip Technology

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DS00002417A-page 31
LAN9220
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is disabled, the EEDIO
and ECLK signals can be used as general-purpose outputs, or they may be used to monitor internal MII signals.
3.9.2.1
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The
operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is pro-
vided below for each operation. Please refer to the E2P_CMD register description in Section 5.3.23, "E2P_CMD –
EEPROM Command Register," on page 89 for E2P_CMD field settings for each command.
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will erase the location
selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms.
FIGURE 3-10:
EEPROM ACCESS FLOW DIAGRAM
FIGURE 3-11:
EEPROM ERASE CYCLE
Idle
Write Data
Regis ter
Write
Command
Regis ter
Read
Command
Regis ter
Bus y Bit = 0
Idle
Write
Command
Regis ter
Read
Command
Regis ter
Read Data
Regis ter
Busy Bit = 0
EEPRO M W rite
EEPRO M Read
1
EECLK
EEDIO (INPUT)
EEDIO (OUTPUT)
EECS
11
A6
A0
t
CSL



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