| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
TMS320DM6431 bảng dữ liệu(PDF) 155 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320DM6431 bảng dữ liệu(HTML) 155 Page - Texas Instruments |
|
155 / 227 page ![]() 6.7.4 Clock PLL Electrical Data/Timing (Input and Output Clocks) MXI/CLKIN 2 3 4 4 5 1 CLK_OUT0 (Divide-by-1) 4 4 2 1 3 TMS320DM6431 Digital Media Processor www.ti.com SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 Table 6-19. Timing Requirements for MXI/CLKIN (-3/-3Q/-3S) Devices(1)(2)(3)(4) (see Figure 6-12) -3/-3Q/-3S NO. UNIT MIN MAX 1 tc(MXI) Cycle time, MXI/CLKIN 33.3 50 ns 2 tw(MXIH) Pulse duration, MXI/CLKIN high 0.45C 0.55C ns 3 tw(MXIL) Pulse duration, MXI/CLKIN low 0.45C 0.55C ns 4 tt(MXI) Transition time, MXI/CLKIN 0.05C ns 5 tJ(MXI) Period jitter, MXI/CLKIN 0.02C ns (1) The MXI/CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for CPU operating frequency. The resulting clock frequency should also meet the PLL requirements discussed in Section 6.7.1, PLL1 and PLL2. For example, for a -3/-3Q/-3S speed device with a 27 MHz CLKIN frequency, the PLL multiply factor should be ≤ 22. To get a ≤ 600 MHz PLL output frequency, SYSCLK1 should be set to a PLL output frequency of divide-by-2 to get ≤ 300 MHz device speed. (2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. (3) For more details on the PLL multiplier factors, see the TMS320DM63x DMP DSP Subsystem Reference Guide (literature number SPRU978). (4) C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns. Figure 6-12. MXI/CLKIN Timing Table 6-20. Switching Characteristics Over Recommended Operating Conditions for CLKOUT0(1)(2) (see Figure 6-13) -3/-3Q/-3S NO. PARAMETER UNIT MIN MAX 1 tC Cycle time, CLKOUT0 33.3 50 ns 2 tw(CLKOUT0H) Pulse duration, CLKOUT0 high 0.45P 0.55P ns 3 tw(CLKOUT0L) Pulse duration, CLKOUT0 low 0.45P 0.55P ns 4 tt(CLKOUT0) Transition time, CLKOUT0 0.05P ns (1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. (2) P = 1/CLKOUT0 clock frequency in nanoseconds (ns). For example, when CLKOUT0 frequency is 27 MHz, use P = 37.04 ns. Figure 6-13. CLKOUT0 Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 155 |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |