TMS320DM6431 datasheet(152/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

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Table 6-15. PLLC1 Clock Frequency Ranges

CLOCK SIGNAL NAME

MIN

MAX

UNIT

MXI/CLKIN(1)

MHz

PLLOUT

At 1.2-V CVDD

300

600

MHz

SYSCLK1 (CLKDIV1 Domain)

-3/-3Q/-3S devices

300

MHz

(1)

MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).

Table 6-16. PLLC2 Clock Frequency Ranges

CLOCK SIGNAL NAME

MIN

MAX

UNIT

MXI/CLKIN(1)

MHz

PLLOUT

At 1.2-V CVDD

300

900

MHz

PLL2_SYSCLK1 (to DDR2 PHY)

266

MHz

(1)

MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).

Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0

transition). The PLL should not be operated until this stabilization time has expired. This stabilization step

must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the

PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see Table 6-17.

The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0)

before bringing the PLL out of reset (writing PLLRST = 1). For the PLL reset time value, see Table 6-17.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1

with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the

PLL lock time value, see Table 6-17.

Table 6-17. PLL1 and PLL2 Stabilization, Lock, and Reset Times

PLL STABILIZATION/LOCK/RESET

MIN

TYP

MAX

UNIT

TIME

PLL Stabilization Time

150

µs

PLL Lock Time

2000C(1)

PLL Reset Time

128C(1)

(1)

C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns.

For details on the PLL initialization software sequence, see theTMS320DM643x DMP DSP Subsystem

Reference Guide (literature number SPRU978).

For more information on the clock domains and their clock ratio restrictions, see Section 6.3.4, DM6431

Power and Clock Domains.

152

Peripheral Information and Electrical Specifications

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