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EPC635 bảng dữ liệu(PDF) 44 Page - Espros Photonics corp |
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EPC635 bảng dữ liệu(HTML) 44 Page - Espros Photonics corp |
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44 / 97 page  Con... Dat... Frames SHUTTER Continuous clock: DCLK is running all the time VSYNC HSYNC DCLK Blanking Valid data Blanking Conversion even R65 Data out R65 Conversion odd R65 Conversion even R64 Conversion odd R64 Integration Init DATA[7:0] & SAT 1st DCS frame of the measurement cycle Processing t SHUTTER t INT t PROC t CONV t HSYNC t SHUTTER_lag Figure 42: Frame timing: Start 1st DCS frame (DCLK: 20MHz) Note: To avoid readout rollover when using slower DCLKs e.g. DCLK < 5MHz with default ROI, pixel_seq_wait_row_done_en must be enabled (refer to chapter 8.7.7). It stretches HSYNC for slower TCMI interfaces. It causes a reduced DCS frame rate due to additional 2µs per ADC conversion (tconv + 2µs). Con... Dat... Frames SHUTTER Continuous clock: DCLK is running all the time VSYNC HSYNC DCLK Blanking Valid data Blanking Conversion even R65 Data out R65 1st Conversion odd R65 Data out R65 2nd Conversion even R64 Conversion odd R64 Data out R6 1st Data out R6 2nd Conversion odd R6 DATA[7:0] & SAT SHUTTER can be kept always “high” or to be applied during last data out for having maximum frame rate nth DCS frame next DCS frame Integration Init Processing Con... Processing t HSYNC_lag t VSYNC_lag t VSYNC t FRAME_continuously Figure 43: Frame timing: Inter frame timing, end of frame and start next frame (DCLK: 20MHz) © 2017 ESPROS Photonics Corporation Characteristics subject to change without notice 44 / 97 Datasheet_epc635-V1.02 www.espros.com |
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