EPC635 datasheet(22/97 Pages) EPC

22 / 97 page

5.3. Supply, Reset and Start-up Options

5.3.1. Supply voltages and external reset

During the power-up sequence, VDD and VDDPLL supplies (Figure 17) must be applied at the same time to the epc635. VDDIO can be

applied either at the same time or after VDD and VDDPLL supplies become stable. In a system where VDDIO voltage is connected in par-

allel to application CPU IO supply pins (see Figure 14), VDD and VDDPLL can be generated by a linear regulator directly from VDDIO sup-

ply. In this case, all these three supplies ramp together.

VDDA and VDDPXH supplies must be applied as a second group, after all VDD, VDDPLL and VDDIO supplies become stable.

The negative supply VBS must be applied after all positive supplies reached their rated levels.

The RESET input must be kept active (low) while all positive voltages are ramping-up in order to guarantee proper reset of all internal cir -

cuits. As soon as rated positive levels are reached, RESET can be released (high). On the other hand, there is no strict relation between

VBS level and RESET timing. Application must guarantee that the VBS supply is turned on and reached its negative rated level before the

chip is triggered via the SHUTTER for frame acquisition. In case of an external clock is applied at XTALIN_CLKIN instead of a crystal/res-

onator is used with on-chip OSC, clock must be present before RESET is released.

IMPORTANT:

■ It is possible to shutdown entire supplies for a very low standby current. In that case, first RESET must be driven low, then supplies must

be turned off in the reverse order. Refer for details to chapter 7.7., Power saving options.

■ VDDA and VDDPXH supplies must be never kept on while turning off VDD, VDDPLL and VDDIO. Such condition may create a perman-

ent damage to the chip.

For rated values of supply voltages, refer to Table 1: Operating conditions and electrical characteristics.

VDD_ramp

VDDPXH

VDD, VDDPLL

VDDIO

VDDA

VBS

VDDIO_ramp

VDDPX_ramp

Positive_supply_ramp

Negative_supply_ramp

DDPLL

Oscillator OSC (XTALIN_CLKIN, XTALOUT)

pll_clk (PLL turn-on)

DDPLL

PLL_lock

DDIO

RESET

EEPROM_to_CFG_copy

RESET

Strap_scan

end of start-up

PLL locked (stable)

SHUTTER

frame

acquisition

all supplies stable

all positive

supplies stable

Figure 17: Start-up and reset sequence during power-up (normal mode)

Characteristics subject to change without notice

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