STA311B datasheet(22/102 Pages) STMICROELECTRONICS

22 / 102 page

Startup/shutdown pop noise removal in SE application

STA311B

22/102

DocID024340 Rev 1

Figure 6. Power-on sequence for pop-free startup

Moreover in order to compensate an internal delay between the tristate signal and the PWM

present in the Power stage devices, the pop noise removal circuit generates a delayed

version of the PWM_in with respect to the Tristate_ramp signal named PWM1_out and

PWM2_out in Figure 6. The delay value delta between the Tristate_ramp and the PWM_in

is programmable using the I²C register 0x80 and the default value is 290 ns.

Finally when the Tristate_ramp duty cycle is equal to 100%, during the de-synchronization

phase the PWM time slots, equal for all the PWMs outputs, are changed so that the final

channel shift will be the one configured by registers 0x33, 0x34, 0x35 and 0x36. At this point

the PWM modulator is automatically un-muted so that the processing outputs can be

played.

6.2

PWM stop

When the EAPD signal is set to zero, the modulator is stopped internally, forcing the input

audio signal, used to feed the modulator, to zero. After that, the PWM which exhibits the

lower PWM timing delay is internally selected and used as a reference. Using the PWM

reference, all the PWMs are re-synchronized, and as soon as all PWMs are aligned, at each

rising edge of a PWM reference, a reverse tristate_ramp signal is generated. As during

startup, the reverse tristate_ramp pulses are centered with respect to the rising and falling

edge of the PWM reference, but in this case the starting duty cycle is equal to 100% and

gradually becomes equal to zero when the reverse tristate_ramp finishes.

In the STA311B the pop-elimination circuit is activated only when at least one channel is set

in binary mode, and the PWMs out speed is set to 384 kHz. In all the other cases the no

pop-free PWM switching start/stop procedure is adopted.

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