STA311B datasheet(19/102 Pages) STMICROELECTRONICS

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STA311B

Serial audio interface

102

4.3

Processing data paths

The whole STA311B processing chain is depicted in Figure 4. A programmable rate

conversion algorithm is applied to the incoming digital audio data (x3,x2,x1,/2) resampling it

to the processing rate. A dual-channel plus line out processing is then implemented, with

mixing, EQ capability followed by a Volume/DRC block and final DC cut filter. The final

oversampling stage and post scaler will provide the output data stream to the PWM

modulators. Three different DRC configurations can be used, single-band, dual-band or

enhanced dual-band DRC, as shown below.

Figure 4. Processing data path

64 * fs

0000

I²S 24-bit data

0100

I²S 20-bit data

1000

I²S 18-bit data

0000

MSB-first I²S 16-bit data

1100

LSB-first I²S 16-bit data

0001

Left-justified 24-bit data

0101

Left-justified 20-bit data

1001

Left-justified 18-bit data

1101

Left-justified 16-bit data

0010

Right-justified 24-bit data

0110

Right-justified 20-bit data

1010

Right-justified 18-bit data

1110

Right-justified 16-bit data

Table 10. Serial audio input formats according to sampling rate (continued)

BICKI

SAI [3:0]

SAIFB

Interface format

1x,2x,4x

Interp

Biquads

B/T

Volume

Limiter

Interp

Distortion

Compensation

C_Con

PWM

FFX

Output

Interp_Rate

8 Inputs

From I2S

DSD

Conversion

6 Inputs

From DSD

Mapping/

Mix #1

DSDE

Mix #2

PreScale

High-Pass

Filter

Biquad

Bass

Hard Set to

-18dB when

AutoMode EQ

(AMEQ)

Hard Set Coeffecients when AutoMode EQ

(AMEQ)

Hard Set

Coeffecients when

AutoMode

Bass Management

Crossover

(AMBMXE)

Hard Set

Coeffecients when

DeEmphasis

Enabled

(DEMP)

From

Mix#1

Engine

Channel

Biquad#10

Output

(CxBLP)

Mix#2

Engine

Treble

User Progammable

Biquad #1 when

High-Pass Bypassed

(HPB)

User Programmable

Biquads #9 and #10

When Tone Bypassed

(CxTCB)

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