ST7DALIF2 datasheet(40/171 Pages) STMICROELECTRONICS

40 / 171 page

Supply, reset and clock management

ST7DALIF2

40/171

9.6.5

Internal watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in

Figure 15.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that

is pulled low during at least tw(RSTL)out.

Figure 15.

RESET sequences

9.7

System integrity management (SI)

The System Integrity Management block contains the Low voltage Detector (LVD) and

Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Illegal Opcode Reset on page 124 for further details.

9.7.1

Low voltage detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the VDD supply

voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well

as the power-down keeping the ST7 in reset.

The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value

for power-on in order to avoid a parasitic reset when the MCU starts running and sinks

current on the supply (hysteresis).

VDD

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

VIT+(LVD)

VIT-(LVD)

th(RSTL)in

RUN

WATCHDOG UNDERFLOW

tw(RSTL)out

RUN

RESET

SOURCE

EXTERNAL

RESET

LVD

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

ACTIVE

PHASE

ACTIVE

PHASE

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