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ST7DALIF2 bảng dữ liệu(PDF) 100 Page - STMicroelectronics

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ST7DALIF2 bảng dữ liệu(HTML) 100 Page - STMicroelectronics

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Serial peripheral interface (SPI)
ST7DALIF2
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17
Serial peripheral interface (SPI)
17.1
Introduction
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves or a
system in which devices may be either masters or slaves.
17.2
Main features
●
Full duplex synchronous transfers (on 3 lines)
●
Simplex synchronous transfers (on 2 lines)
●
Master or slave operation
●
Six master mode frequencies (fCPU/4 max.)
●
fCPU/2 max. slave mode frequency (see note)
●
SS Management by software or hardware
●
Programmable clock polarity and phase
●
End of transfer interrupt flag
●
Write collision, Master Mode Fault and Overrun flags
Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
17.3
General description
Figure 45 shows the serial peripheral interface (SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through 3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and input by SPI slaves
–SS: Slave select:
This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves
individually and to avoid contention on the data lines. Slave SS inputs can be driven
by standard I/O ports on the master device.



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