ST7DALIF2 datasheet(77/171 Pages) STMICROELECTRONICS

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ST7DALIF2

12-bit autoreload timer 2 (AT2)

77/171

14.4

Low power modes

14.5

Interrupts

14.6

14.6.1

Timer control status register (ATCSR)

Read / Write

Reset Value: 0x00 0000 (x0h)

Bit 7 = Reserved.

Bit 6 = ICF Input Capture Flag.

This bit is set by hardware and cleared by software by reading the ATICR register (a read

access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit

value.

0: No input capture

1: An input capture has occurred

Bit 5 = ICIE IC Interrupt Enable.

This bit is set and cleared by software.

0: Input capture interrupt disabled

1: Input capture interrupt enabled

Table 36.

Effect of low power modes on AT2 timer

Mode

Description

Slow

The input frequency is divided by 32

Wait

No effect on AT timer

Active-halt

AT timer halted except if CK0=1, CK1=0 and OVFIE=1

Halt

AT timer halted

Table 37.

AT2 timer interrupt control bits

Interrupt event(1)

The CMP and IC events are connected to the same interrupt vector. The OVF event is mapped on a

separate vector (see Table 15: Interrupt mapping). They generate an interrupt if the enable bit is set in the

ATCSR register and the interrupt mask in the CC register is reset (RIM instruction).

Event

flag

Enable

control

bit

Exit

from

Wait

Exit

from

Halt

Exit

from

Active-halt

Overflow event

OVF

OVIE

Yes

Yes(2)

Only if CK0=1 and CK1=0 (fCOUNTER = fLTIMER)

IC event

ICF

ICIE

Yes

CMP event

CMPF0

CMPIE

Yes

ICF

ICIE

CK1

CK0

OVF

OVFIE

CMPIE

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