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L6751C bảng dữ liệu(PDF) 45 Page - STMicroelectronics |
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L6751C bảng dữ liệu(HTML) 45 Page - STMicroelectronics |
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45 / 57 page ![]() DocID025037 Rev 1 45/57 L6751C System control loop compensation 57 11 System control loop compensation The control system can be modeled with an equivalent single-phase converter with the only difference being the equivalent inductor L/N (where each phase has an L inductor and N is the number of the configured phases), see Figure 15. Figure 15. Equivalent control loop The control loop gain results (obtained opening the loop after the COMP pin): Equation 21 where: RLL is the equivalent output resistance determined by the droop function (voltage positioning) ZP(s) is the impedance resulting from the parallel of the output capacitor (and its ESR) and the applied load RO ZF(s) is the compensation network impedance ZL(s) is the equivalent inductor impedance A(s) is the error amplifier gain is the PWM transfer function. The control loop gain is designed in order to obtain a high DC gain to minimize static error and to cross the 0 dB axes with a constant -20 dB/dec slope with the desired crossover frequency T. Neglecting the effect of ZF(s), the transfer function has one zero and two poles; both poles are fixed once the output filter is designed (LC filter resonance LC) and the zero ( ESR) is fixed by ESR and the droop resistance. Ref COMP RF CF RFB PWM L/N ESR CO d VCOMP VOUT ZF(s) ZFB(s) FBR RGND AM14821v1 GLOOP s PWM ZF s R LL ZP s + ZP s Z L s + ZF s As -------------- 1 1 As ------------ + R FB + ------------------------------------------------------------------------------------------------------------------- – = PWM 9 10 ------ VIN V OSC ------------------- = |
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