L6751C datasheet(42/57 Pages) STMICROELECTRONICS

42 / 57 page

Efficiency optimization

L6751C

42/57

DocID025037 Rev 1

9.2

Variable frequency diode emulation (VFDE)

As the current required by the load is reduced, the L6751C progressively reduces the

number of switching phases according to DPM settings on the multi-phase section. If single-

phase operation is configured, when the delivered current approaches the CCM/DCM

boundary, the controller enters VFDE operation. The single-phase section, being a single-

phase, enters VFDE operation always when the delivered current approaches the

CCM/DCM boundary.

In a common single-phase DC-DC converter, the boundary between CCM and DCM is

when the delivered current is perfectly equal to 1/2 of the peak-to-peak ripple into the

inductor (Iout = Ipp/2). Further decreasing the load in this condition maintaining CCM

operation would cause the current into the inductor to reverse, therefore sinking current

from the output for a part of the off-time. This results in a poorly efficient system.

The L6751C device is able (via the CSPx/CSNx pins) to detect the sign of the current across

the inductor (zero cross detection, ZCD), so it is able to recognize when the delivered

current approaches the CCM/DCM boundary. In VFDE operation, the controller fires the

high-side MOSFET for a TON and the low-side MOSFET for a TOFF (the same as when the

controller works in CCM mode) and waits the necessary time until next firing in high

impedance (Hi-Z). The consequence of this behavior is a linear reduction of the “apparent”

switching frequency that, in turn, results in an improvement of the efficiency of the converter

when in very light load conditions.

The “apparent” switching frequency reduction is limited to 30 kHz so as not to enter the

audible range.

9.3

VFDE and DrMOS

To guarantee correct behavior for the DrMOS power stage compliant with Intel specification

rev3, it is recommended to control the DrMOS’ SMOD input through the ENDRV/SENDRV

pins of the L6751C. DrMOS enable must be controlled with the same signal used for the

L6751C EN pin.

Proper Hi-Z level can be programmed by adding proper external resistor divider across

PWM1 and PWM2. See Section 4.2 on page 20 for details about Hi-Z level recognition. See

reference schematic in Figure 1 on page 6.

Figure 12. Output current vs. switching frequency in PSK mode

Iout = Ipp/2

Iout < Ipp/2

Tsw

Tvfde

AM14819v1

L6751C bảng dữ liệu(PDF) 42 Page - STMicroelectronics

L6751C bảng dữ liệu(HTML) 42 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

bảng dữ liệu tải về

Link URL