L6751C datasheet(32/57 Pages) STMICROELECTRONICS

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Output voltage positioning

L6751C

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DocID025037 Rev 1

transition and re-activated with proper delay after the end of the transition to prevent from

false triggering.

6.8

LSLESS startup and pre-bias output

Any time the device resumes from an “OFF” code and at the first power-up, in order to avoid

any kind of negative undershoot on the load side, the L6751C performs a special sequence

in enabling the drivers: during the soft-start phase, the LS driver results as being disabled

(LS = OFF - PWMx set to Hi-Z and ENDRV = 0) until the first PWM pulse. After the first

PWM pulse, PWMx outputs switch between logic “0” and logic “1” and ENDRV is set to logic

“1”.

This particular sequence avoids the dangerous negative spike on the output voltage that

can occur if starting over a pre-biased output.

Low-side MOSFET turn-on is masked only from the control loop point of view: protection is

still allowed to turn on the low-side MOSFET if overvoltage is needed.

6.9

DVID optimization: REF/SREF

High slew rate for dynamic VID transitions causes undershoot on the regulated voltage,

causing violation in the microprocessor requirement. To compensate this behavior and to

remove any undershoot in the transition, each section features a DVID optimization circuit.

The reference used for the regulation is available on the REF/SREF pin (see Figure 10).

Connect an RREF/CREF to GND (RSREF/CSREF for the single-phase) to optimize the DVID

behavior. Components may be designed as follows (multi-phase, the same equations apply

to single-phase):

Equation 10

where

Vosc is the PWM ramp and kV the gain for the voltage loop (see Section 11 on page

45).

Figure 8. LSLESS startup: enabled (left)

Figure 9. LSLESS startup: disabled (right)

CREF

CF 1

V

OSC

kV VIN



--------------------

–







RREF

RF CF



CREF

-------------------

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