VITESSE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

G52268-0, Rev 3.3

Page 23

04/10/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Figure 19: RCLK and RCLKN Timing Waveforms with DUAL = 1

Table 14: General Receive AC Characteristics

NOTE: (1) The probability of correct data acquisition and recovery is 95% per FC-PH 4.3 Section 5.3.

Parameters

Description

Min.

Max.

Units

Conditions

Delay between rising edge of

RCLK to rising edge of

RCLKN

-500

+500

ps

incoming data on Rx.

RCLK to RCLKN skew

-500

500

ps

Deviation of RCLK rising

edge to RCLKN rising edge.

Nominal delay is 10-bit

times.

Period of RCLK and

RCLKN

0.49 x

0.51 x

ps

Whether or not locked to

serial data, independent of

DUAL input.

Deviation of

RCLK/RCLKN period from

REFCLK period

-1.0

1.0

%

Whether or not locked to

serial data, independent of

DUAL input.

Output rise and fall time

—

2.4

ns

Latency from RX0 to

REFCLK or RCLK

70.5bc-1.6ns

48.5bc-1.6ns

81.5bc+4.1ns

102.5bc+4.1ns

bc+ns

ENDEC=1, recenter only

ENDEC=X, recenter + drift

(1)

Data acquisition lock time

—

2500

bc

8B/10B IDLE pattern,

Tested on a sample basis.

Receive data Total

Jitter Tolerance (p-p)

—

600

ps

IEEE 802.3z Clause 38.68,

tested on a sample basis.

Receive data Deterministic

Jitter Tolerance (p-p)

—

370

ps

IEEE 802.3z Clause 38.69,

tested on a sample basis.

RCLKN

RCLK

Delay

10

f

baud

------------

∆T

3

±

=

T

RC LK

T

REFC LK

∆T

4

±

=