VITESSE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

G52268-0, Rev 3.3

Page 7

04/10/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Receiver Functional Description

Serial Data Source

The receiver has both primary and redundant serial input ports, PRX and RRX, respectively, which consist

of differential PECL input buffers. It also has a control input, RXP/R, used to select either the primary or

redundant serial input as the data source. When RXP/R is HIGH, the serial data source is PRX. When

LBEN(1:0)=10, the transmitter is looped back and becomes the serial data source regardless of the state of

RXP/R (see Table 4).

Table 4: Serial Data Source Selection

Signal Detection

The primary and redundant PECL input buffers have an associated signal detect output, PSDET and

RSDET. Both outputs are available for continuous monitoring of the selected and non-selected input. Each

signal detect output is asserted HIGH when transitions are detected on the associated PECL input and the signal

amplitude exceeds 200mV. A LOW indicates that either no transitions are detected or the signal amplitude is

below 100mV. The signal detect outputs are considered undefined when the signal amplitude is in the 100mV to

200mV range. The signal detect circuitry behaves like a re-triggerable one shot that is triggered by signal

transitions, and whose time-out interval ranges from 40 to 80 bit times. The transition density is not checked to

make sure that it corresponds to a valid Fibre Channel data stream. The PSDET and RSDET output timing is

identical to the low-speed receiver outputs, as selected by RMODE(1:0) in Table 5.

Receiver Equalization

Incoming data on the PRX/RRX input typically contains a substantial amount of Inter Symbol Interference

(ISI) or deterministic jitter which reduces the ability of the receiver to recover data without errors. An equalizer

has been added to each of the receiver’s input buffers in order to compensate for this deterministic jitter. This

circuit has been designed to effectively reduce the ISI commonly found in copper cables or backplane traces due

to low frequencies traveling faster than high frequencies as a result of the skin effect. The equalizer boosts high

frequency edge response in order to reduce the adverse effects of ISI.

LBEN(1:0)

RXP/R

Serial Data Source

≠ 1 0

0

RRX

≠ 1 0

1

PRX

= 1 0

X

LBTX (Loopback from PTX/RTX)