ESE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

Page 12

G52268-0, Rev 3.3

04/10/01

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Within the receiver there are elastic buffers used to deskew multiple VSC7212s and/or VSC7216s in order

to align them to a common word clock. The receiver’s elastic buffer allows the chips’ input to be skewed up to

+/-7 bit times in order to accommodate circuit imperfections, differences in transmission delay and jitter.

Multiple devices can be used in synchronous operation if the skew between all serial input pairs is maintained

less than +/-7 serial clock bit times. This allows easy implementation of robust systems.

Chip-to-Chip word alignment is enabled by connecting the WSI input of all devices to the WSO output of

an arbitrarily selected “Master” device. The FLOCK input state and WSI input source determine whether or not

rate matching (IDLE deletion or duplication) will be performed. Chip-to-chip alignment is disabled when WSI

is not connected to a WSO output. Rate matching is disabled when either FLOCK is HIGH or WSI is held LOW

(see Table 6).

In order to perform word alignment, a synchronization point must be seen across all receivers to be aligned

within the +/-7 bit time window. The VSC7212 receiver recognizes the first four characters of the Word Sync

Sequence (either K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+) as the synchronization

point. As a model for understanding, consider the case where two VSC7212 transmitters send 16 bits of data to

two receivers via copper media which has small cable length differences causing chip-to-chip skew. Both

transmitters must be word aligned by simultaneously sending the Word Sync Sequence (within the +/-7 bit

window). On detection of the synchronization point, the receivers will reposition the recovered data within their

elastic buffers in order to align both devices and remove any chip-to-chip skew. All normal data characters

following the Word Sync Sequence will be properly chip-to-chip word aligned. In the process of alignment, one

or two of the final twelve K28.5 characters in the Word Sync Sequence may be deleted or duplicated.

The VSC7212 is capable of performing rate matching in multiple device applications by inserting or

deleting IDLEs in parallel across all receivers. This requires that the chip-to-chip aligned data streams contain

IDLEs inserted simultaneously on all transmitters according to the IDLE density requirement previously

described.

Table 6: Word Alignment and Rate Matching Control

FLOCK

WSI Source

Chip-to-Chip Alignment

Rate Matching

0

0

Off

Off

0

It’s own WSO

or 1

Off

Enabled within chip

0

Another chips’ WSO

Enabled

Enabled between chips

1

0

Off

Off

1

1

Off

Off

1

Another chips’

WSO

Enabled

Off