PC87332VLJ datasheet(12/98 Pages) NSC

12 / 98 page

10 Pin Description (Continued)

Symbol

Function

IDEHI

IDE High Byte

This output enables the high byte data latch during a read or write to the hard drive if

the hard drive returns IOCS16 This output is inactive if the IDE interface is disabled via the

Configuration Register (See VLD0 for further information)

IDELO

IDE Low Byte

This output enables the low byte data latch during a read or write to the hard drive This

output is inactive if the IDE interface is disabled via the Configuration Register (See BADDR0 for

further information)

IDENT

Identity

During chip reset the IDENT and MFM pins are sampled to determine the desired mode of

operation according to the following table

IDENT

MFM

MODE

1 or NC

PC-AT Mode

Illegal

1 or NC

PS2 Mode

Model 30 Mode

AT Mode

The DMA enable bit in the DOR is valid TC is active high Status Registers A and B are

disabled (TRI-STATE)

Model 30 Mode

The DMA enable bit in the DOR is valid TC is active high Status Registers A and B

are enabled

PS2 Mode

The DMA enable bit in the DOR is a don’t care and the FDRQ and IRQ6 signals are

always enabled TC is active low Status Registers A and B are enabled

After chip reset the state of IDENT determines the polarity of the DENSEL output When IDENT is a

logic ‘‘1’’ DENSEL is active high for the 500 kbps1 Mbps2 Mbps data rates When IDENT is a logic

‘‘0’’ DENSEL is active low for the 500 kbps1 Mbps2 Mbps data rates (See Mode command for

further explanation of DENSEL)

IDLE

This pin is IDLE output when bit 4 of PMC is 1 IDLE indicates that the FDC is in the IDLE state

and can be powered down Whenever the FDC is in IDLE state or whenever the FDC is in power-down

state the pin is active high This bit is MTR1 when bit 4 of the Power Management Control Register

(PMC) is 0

INDEX

Normal

Index

This input signals the beginning of a FDD track

Mode

INDEX

PPM

Index

This pin provides an additional Index signal in PPM Mode when PNF e 0

Mode

(See PD0 and Table 7-5 for further information)

INIT

Initialize

When this signal is low it causes the printer to be initialized This pin is in a TRI-STATE

condition 10 ns aftera1is loaded into the corresponding Control Register bit The system should pull

this pin high using a 47 kX resistor (See DIR and Table 7-5 for further information)

IOCHRDY

IO Channel Ready

This is the IO Channel Ready open drain output when bit 7 of FCR is 0 When

IOCHRDY is driven low the EPP extends the host cycle This pin is the MFM output pin when bit 7 of

FCR is 1 (See MFM pin for further information)

IOCS16

IO Chip Select 16-bit

This input is driven by the peripheral device when it can accommodate a 16-bit

access

IRQ34

1 100

Interrupt 3 and 4

These are active high interrupts associated with the serial ports IRQ3 presents the

signal if the serial port has been designated as COM2 or COM4 IRQ4 presents the signal if the serial

port is designated as COM1 or COM3 The appropriate interrupt goes active whenever it is enabled via

the Interrupt Enable Register (IER) the associated Interrupt Enable bit (Modem Control Register bit 3

MCR3) and any of the following conditions are active Receiver Error Receive Data available

Transmitter Holding Register Empty or a Modem Status Flag is set The interrupt is reset low (inactive)

after the appropriate interrupt service routine is executed after being disabled via the IER or after a

Master Reset Either interrupt can be disabled putting them into TRI-STATE by setting the MCR3 bit

low

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