PC87332VLJ datasheet(80/98 Pages) NSC

80 / 98 page

70 Parallel Port (Continued)

711 CONFIGURATION REGISTERS ACCESS (Mode 111)

The two configuration registers CNFGA and CNFGB are

accessible only in this mode

712 INTERRUPT GENERATION

An interrupt is generated when any of the following events

occur

1 When bit 2 of ECR is 0 bit 3 of ECR is 1 and TC is

asserted during the ECP DMA cycle

2 When bit 2 of ECR is 0 bit 3 of ECR is 0 bit 5 of DCR is 0

and there are eight or more bytes free in the FIFO It

includes the case when bit 2 of ECR is cleared to 0 and

there are already eight or more bytes free in the FIFO

(modes 010 011 and 110 only)

3 When bit 2 of ECR is 0 bit 3 of ECR is 0 bit 5 of DCR is 1

and there are eight or more bytes to be read from the

FIFO It includes the case when bit 2 of ECR is cleared to

0 and there are already eight or more bytes to be read

from the FIFO (modes 011 and 110 only)

4 When bit 4 of ECR is 0 and ERR is asserted (high to low

edge) or ERR is asserted when bit 4 of ECR is modified

from1to0

5 When bit 4 of DCR is 1 and ACK is deasserted (low-to-

high edge)

The interrupt is generated according to bits 5 and 6 of the

PCR

Note

Interrupt events

3 and

4 are level events thus they are

shaped as interrupt pulses These interrupts are masked (inactive)

when the ECP clock is frozen Interrupt event

1 is a pulse event

The last interrupt event behaves as in the normal SPP mode the IRQ

signal follows the ACK signal transition (when bit 5 of PCR is 0 and bit

6 of PCR is 0) Note that interrupt event

4 may be lost when the

ECP clock is frozen

80 Integrated Device Electronics

Interface (IDE)

81 INTRODUCTION

Another key interface for PC design is facilitated through the

use of the PC87332 IDE (Integrated Drive Electronics) Hard

Disk interface Only three buffer chips are required to con-

struct the IDE Hard Disk Interface circuit

The IDE interface is essentially the AT bus ported to the

hard drive The hard disk controller resides on the hard drive

itself So the IDE interface circuit must provide the AT bus

signals including data bits D15 – 0 address lines A3 – 0 as

well as the common control signals

82 IDE SIGNALS

Using ’LS244 devices in the IDE interface provides buffering

of the control and address lines Four control signals IDEHI

IDELO HCS0 HCS1 one status signal IOCS16 and one

data signal IDED7 are required by the IDE interface The

PC87332 provides all of these signals They are summa-

rized below

IDEHI enables an ’LS245 octal bus transceiver for the upper

data lines (D15 – 8) during 16-bit read and write operations

at addresses 1F0 – 1F7 IDEHI will activate the ’LS245 only if

the IOCS16 output from the hard drive is active IDELO en-

ables another ’LS245 octal bus transceiver for the lower

data lines (D7 – 0) during all (1F0 – 1F7 3F6 and 3F7) reads

and writes

The IDED7 signal insures that the D7 data bus signal line is

disabled for address 3F7 (this bit is used for the Disk

Changed register on the floppy disk controller at that ad-

dress)

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