PC87332VLJ datasheet(64/98 Pages) NSC

64 / 98 page

50 FDC Functional Description (Continued)

Specify command values will be don’t cares so they must

be reinitialized The major default conditions are FIFO dis-

abled FIFO threshold e 0 Implied Seeks disabled and

Drive Polling enabled

A software reset can be performed through the Digital Out-

put Register or Data Rate Select Register The DSR reset

bit is self-clearing while the DOR reset bit is not self-clear-

ing If the LOCK bit in the Lock command was set to a 1

previous to the software reset the FIFO THRESH and

PRETRK parameters in the Configure command will be re-

tained In addition the FWR FRD and BST parameters in

the Mode command will be retained if LOCK is set to 1 This

function eliminates the need for total reinitialization of the

controller after a software reset

After a hardware (assuming the FDC is enabled in the FER)

or software reset the Main Status Register is immediately

available for read access by the mP It will return a 00h value

until all the internal registers have been updated and the

data separator is stabilized When the controller is ready to

receive a command byte the MSR will return a value of 80h

(Request for Master bit is set) The MSR is guaranteed to

return the 80h value within 25 ms after a hardware or soft-

ware reset All other user addressable registers other than

the Main Status Register and Data Register (FIFO) can be

accessed at any time even while the part is in reset

60 Serial Ports

Each of these serial ports functions as a serial data input

output interface in a microcomputer system The system

software determines the functional configuration of the

UARTs via an 8-bit bidirectional data bus

The UARTs are completely independent They perform

serial-to-parallel conversion on data characters received

from a peripheral device or a MODEM and parallel-to-serial

conversion on data characters received from the CPU The

CPU can read the complete status of either UART at any

time during the functional operation Status information re-

ported includes the type and condition of the transfer opera-

tions being performed by the UART as well as any error

conditions (parity overrun framing or break interrupt)

The UARTs have programmable baud rate generators that

are capable of dividing the internal reference clock by divi-

sors of 1 to (216 – 1) and producing a 16x clock for driving

the transmitter logic Provisions are also included to use this

16x clock to drive the receiver logic The UARTs have com-

plete MODEM-control capability and a prioritized interrupt

system Interrupts can be programmed to the user’s require-

ments minimizing the computing required to handle the

communications link

61 SERIAL PORT REGISTERS

Two identical register sets one for each channel are in the

PC87332 All register descriptions in this section apply to

the register sets in both channels See Table 6-1

62 LINE CONTROL REGISTER (LCR)

ReadWrite

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit

This is a read and write register Table 6-2 shows the con-

tents of the LCR Details on each bit follow

TLC11930 – 11

FIGURE 6-1 PC87332 Composite Serial Data

TABLE 6-1 PC87332 UART

DLAB

Selected Register

Receiver Buffer (Read)

Transmitter Holding (Write)

Interrupt Enable

Interrupt Identification (Read)

FIFO Control (Write)

Line Control

MODEM Control

Line Status

MODEM Status

Scratch

Divisor Latch

(Least Significant Byte)

Divisor Latch

(Most Significant Byte)

Bits 01

These two bits specify the number of data bits in

each transmitted or received serial character The

encoding of bits 0 and 1 is as follows

Bit 1

Bit 0

Data Length

5 Bits

6 Bits

7 Bits

8 Bits

Bit 2

This bit specifies the number of Stop bits transmit-

ted with each serial character If it is 0 one Stop

bit is generated in the transmitted data If it is 1

when a 5-bit data length is selected one and a

half Stop bits are generated If it is 1 when either a

6- 7- or 8-bit word length is selected two Stop

bits are generated The receiver checks the first

Stop bit only regardless of the number of Stop

bits selected

Bit 3

This bit is the Parity Enable bit When it is 1 a

Parity bit is generated (transmit data) or checked

(receive data) between the last data bit and the

following Stop bit of the serial data (The Parity bit

is used to produce an even or odd number of 1s

when the data bits and the Parity bit are summed)

Bit 4

This bit is the Even Parity Select bit When parity is

enabled and bit 4 is 0 an odd number of logic 1s

is transmitted or checked in the data word bits and

Parity bit When parity is enabled and bit 4 is a 1

an even number of logic 1s is transmitted or

checked

Bit 5

This bit is the Stick Parity bit When parity is en-

abled it is used in conjunction with bit 4 to select

Mark or Space Parity When LCR bits 3 4 and 5

are 1 the Parity bit is transmitted and checked as a

0 (Space Parity) If bits 3 and 5 are 1 and bit 4 is a

0 then the Parity bit is transmitted and checked as

1 (Mark Parity) If bit 5 is 0 Stick Parity is disabled

PC87332VLJ bảng dữ liệu(PDF) 64 Page - National Semiconductor (TI)

PC87332VLJ bảng dữ liệu(HTML) 64 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

bảng dữ liệu tải về

Link URL