PC87332VLJ datasheet(69/98 Pages) NSC

69 / 98 page

60 Serial Ports (Continued)

67 INTERRUPT ENABLE REGISTER (IER)

This register enables the five types of UART interrupts

Each interrupt can individually activate the appropriate inter

rupt (IRQ3 or IRQ4) output signal It is possible to totally

disable the interrupt system by resetting bits 0 through 3 of

the Interrupt Enable Register (IER) Similarly setting bits of

this register to 1 enables the selected interrupt(s) Disabling

an interrupt prevents it from being indicated as active in the

IIR and from activating the interrupt output signal All other

system functions operate in their normal manner including

the setting of the Line Status and MODEM Status Registers

Table 6-2 shows the contents of the IER Details on each bit

follow See MODEM Control Register bit 3 for more informa-

tion on enabling the interrupt pin

Bit 0

When set to 1 this bit enables the Received Data

Available Interrupt and Timeout Interrupt in the

FIFO Mode

Bit 1

This bit enables the Transmitter Holding Register

Empty Interrupt when set to 1

Bit 2

This bit enables the Receiver Line Status Inter-

rupt when set to logic 1

Bit 3

This bit enables the MODEM Status Interrupt

when set to logic 1

Bits 4 – 7

These four bits are always logic 0

68 MODEM CONTROL REGISTER (MCR)

This register controls the interface with the MODEM or data

set (or a peripheral device emulating a MODEM) The con-

tents of the MODEM Control Register (MCR) are indicated

in Table 6-2 and are described as follows

Bit 0

This bit controls the Data Terminal Ready (DTR)

output When it is set to 1 the DTR output is

forced to a logic 0 When it is reset to 0 the DTR

output is forced to 1 In Local Loopback Mode

this bit controls bit 5 of the MODEM Status Regis-

ter

Note

The DTR and RTS output of the UART may be applied

to an EIA inverting line driver (such as the DS1488) to

obtain the proper polarity input at the MODEM or data

set

Bit 1

This bit controls the Request to Send (RTS) out-

put Its effect on the RTS output is identical to that

described above for bit 0 In Local Loopback

Mode this bit controls bit 4 of the MODEM Status

Bit 2

This bit is the OUT1 bit It does not have an output

pin associated with it It can be written to and read

by the CPU In Local Loopback Mode this bit con-

trols bit 6 of the MODEM Status Register

Bit 3

This bit enables the interrupt when set No exter-

nal pin is associated with this bit other than IRQ3

4 In Local Loopback Mode this bit controls bit 7

of the MODEM Status Register

Bit 4

This bit provides a Local Loopback feature for di-

agnostic testing of the UART When it is set to 1

the following changes take place the transmitter

Serial Output (SOUT) is set to the Marking (1)

state the receiver Serial Input (SIN) is disconnect-

ed the output of the Transmitter Shift Register is

‘‘looped back’’ (connected) to the Receiver Shift

CTS RI and DCD) are disconnected and the

DTR RTS OUT1 IRQ ENABLE bits in MCR are

internally connected to DSR CTS RI and DCD in

MSR respectively The MODEM Control output

pins are forced to their high (inactive) states In the

Loopback Mode data that is transmitted is imme-

diately received This feature allows the processor

to verify the transmit-and-received-data paths of

the serial port

In the Loopback Mode the receiver and transmit-

ter interrupts are fully operational The MODEM

Status Interrupts are also operational but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register The IRQ3

and IRQ4 pins will be at TRI-STATE in the Loop-

back Mode

Bits 5 – 7

These bits are permanently set to 0

69 MODEM STATUS REGISTER (MSR)

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU In addi-

tion to this current-state information

four bits of the

MODEM Status Register provide change information These

bits are set to a logic 1 whenever a control input from the

MODEM changes state They are reset to logic 0 whenever

the CPU reads the MODEM Status Register Table 6-2

shows the contents of the MSR Details on each bit follow

Bit 0

This bit is the Delta Clear to Send (DCTS) indicator

It indicates that the CTS input to the chip has

changed state since the last time it was read by the

CPU

Bit 1

This bit is the Delta Data Set Ready (DDSR) indica-

tor It indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU

Bit 2

This bit is the Trailing Edge of Ring Indicator (TERI)

detector It indicates that the RI input to the chip has

changed from a low to a high state

Bit 3

This bit is the Delta Data Carrier Detect (DDCD) in-

dicator It indicates that the DCD input to the chip

has changed state

Note

Whenever bit 0 1 2 or 3 is set to logic 1 a MODEM Status

Interrupt is generated

Bit 4

This bit is the complement of the Clear to Send

(CTS) input If bit 4 (loopback) of the MCR is set to

1 this bit is equivalent to RTS in the MCR

Bit 5

This bit is the complement of the Data Set Ready

(DSR) input If bit 4 of the MCR is set to 1 this bit is

equivalent to DTR in the MCR

Bit 6

This bit is the complement of the Ring Indicator (RI)

input If bit 4 of the MCR is set to 1 this bit is equiva-

lent to OUT1 in the MCR

Bit 7

This bit is the complement of the Data Carrier De-

tect (DCD) input If bit 4 of the MCR is set to 1 this

bit is equivalent to IRQ ENABLE in the MCR

610 SCRATCHPAD REGISTER (SCR)

This 8-bit ReadWrite Register does not control the UART

in any way It is intended as a scratchpad register to be used

by the programmer to hold data temporarily

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