STA333IS datasheet(20/43 Pages) STMICROELECTRONICS

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STA333IS

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DocID022855 Rev 3

5.1

Configuration registers (addr 0x00 to 0x05)

5.1.1

Configuration register A (addr 0x00)

Master clock select

The STA333IS supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:

•

32.768 MHz for 32 kHz

•

45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

•

49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input

sampling frequency (fS).

The relationship between the input clock and the input sampling rate is determined by both

the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor

generating the internal clock and the IR bit determines the oversampling ratio used

internally.

FDRB

TWAB

TWRB

IR1

IR0

MCS2

MCS1

MCS0

Table 9. Master clock select

Bit

R/W

RST

Name

Description

0R/W

1MCS0

Master clock select: Selects the ratio between the

input I2S sampling frequency and the input clock.

1R/W

1MCS1

2R/W

0MCS2

Table 10. MCS bits

Input sampling rate

fS (kHz)

MCS[2:0]

101

100

011

010

001

000

32, 44.1, 48

576 * fS

128 * fS

256 * fS

384 * fS 512 * fS 768 * fS

88.2, 96

64 * fS

128 * fS

192 * fS 256 * fS 384 * fS

176.4, 192

32 * fS

64 * fS

96 * fS 128 * fS 192 * fS

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