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STA333IS bảng dữ liệu(PDF) 17 Page - STMicroelectronics |
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STA333IS bảng dữ liệu(HTML) 17 Page - STMicroelectronics |
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17 / 43 page ![]() DocID022855 Rev 3 17/43 STA333IS I2C bus specification 4.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA333IS acknowledges this and then waits for the byte of internal address. After receiving the internal byte address, the STA333IS again responds with an acknowledgement. 4.3.1 Byte write In the byte write mode the master sends one data byte which is acknowledged by the STA333IS. The master then terminates the transfer by generating a STOP condition. 4.3.2 Multi-byte write The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer. Figure 8. Write-mode sequence 4.4 Read operation 4.4.1 Current address byte read Following the START condition the master sends a device select code with the RW bit set to 1. The STA333IS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 4.4.2 Current address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA333IS. The master acknowledges each data byte read and then generates a STOP condition, terminating the transfer. 4.4.3 Random address byte read Following the START condition the master sends a device select code with the RW bit set to 0. The STA333IS acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA333IS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333IS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. DEV-ADDR ACK START RW SUB-ADDR ACK DATAIN ACK STOP BYTE WRITE DEV-ADDR ACK START RW SUB-ADDR ACK DATAIN ACK STOP MULTIBYTE WRITE DATAIN ACK |
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