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LPC47M172 bảng dữ liệu(PDF) 88 Page - SMSC Corporation

tên linh kiện LPC47M172
Giải thích chi tiết về linh kiện  ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
PDF  227 Pages
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nhà sản xuất  SMSC [SMSC Corporation]
Trang chủ  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M172 bảng dữ liệu(HTML) 88 Page - SMSC Corporation

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Page 88
SMSC LPC47M172
DATASHEET
Note 1
DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 2
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 3
When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Note 4
This bit no longer has a pin associated with it.
Note 5
When operating in the XT mode, this register is not available.
Note 6
These bits are always zero in the non-FIFO mode.
Note 7
Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 8
The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime
register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).



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