LPC47M172 datasheet(41/227 Pages) SMSC

41 / 227 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)

Page 41

SMSC LPC47M172

DATASHEET

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a

hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic “1”.

BIT 7 RESERVED

Always read as a logic “1”

PS/2 Model 30 Mode

nDRV2

nDS1

nDS0

WDATA

F/F

RDATA

F/F

WGATE

F/F

nDS3

nDS2

RESET

COND.

N/A

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported.

BIT 1 nDRIVE SELECT 3

The DS3 disk interface is not supported.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of

WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of

RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of

WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input. Note: This function is not supported.

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