LPC47M172 datasheet(52/227 Pages) SMSC

52 / 227 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)

Page 52

SMSC LPC47M172

DATASHEET

RESET

There are three sources of system reset on the FDC: the nPCI_RESET pin, a reset generated via a bit in

the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC.

All resets take the FDC out of the power down state.

All operations are terminated upon a nPCI_RESET, and the FDC enters an idle state. A reset while a disk

write is in progress will corrupt the data and CRC.

On exiting the reset state, various internal registers are cleared, including the Configure command

information, and the FDC waits for a new command. Drive polling will start unless disabled by a new

Configure command.

nPCI_RESET Pin (Hardware Reset)

The nPCI_RESET pin is a global reset and clears all registers except those programmed by the Specify

command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state.

DOR Reset vs. DSR Reset (Software Reset)

These two resets are functionally the same. Both will reset the FDC core, which affects drive status

information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires

the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set

automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset

state.

6.5

Modes of Operation

The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are

determined by the state of the Interface Mode bits in FDC logical device -CRF0[3,2].

6.5.1

PC/AT Mode

The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt

and DMA functions), and DENSEL is an active high signal.

6.5.2

PS/2 Mode

This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR

becomes a “don’t care”. The DMA and interrupt functions are always enabled, and DENSEL is active low.

6.5.3

Model 30 Mode

This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR

becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.

6.6

DMA Transfers

DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA

request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer

modes: Single Transfer and Burst Transfer. Burst mode is enabled via FDC Logical Device -CRF0-Bit[1].

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