LPC47M172 datasheet(4/227 Pages) SMSC

4 / 227 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)

Page 4

SMSC LPC47M172

DATASHEET

Table Of Contents

LPC47M172 Datasheet Revision History ................................................................................................. 3

Chapter 1

General Description.............................................................................................................. 12

Chapter 2

Pin Layout ............................................................................................................................ 13

Chapter 3

Description of Pin Functions ................................................................................................ 15

3.1

Buffer Name Descriptions ..........................................................................................................................23

3.2

Pins With Internal Resistors .......................................................................................................................24

3.3

Pins That Require External Resistors.........................................................................................................24

3.4

Default State of Pins...................................................................................................................................25

Chapter 4

Block Diagram ...................................................................................................................... 29

Chapter 5

Power and Clock Functionality............................................................................................. 30

5.1

3 Volt Operation / 5 Volt Tolerance ............................................................................................................30

5.2

VCC Power ................................................................................................................................................30

5.3

VTR Power.................................................................................................................................................30

5.3.1

Trickle Power Functionality .................................................................................................................31

5.4

V5P0_STBY Power ....................................................................................................................................31

5.5

32.768 kHz Trickle Clock Input...................................................................................................................31

5.5.1

Indication of 32KHZ Clock...................................................................................................................31

5.6

14.318 MHz Clock Input .............................................................................................................................32

5.7

Internal PWRGOOD...................................................................................................................................32

5.8

Maximum Current Values...........................................................................................................................32

5.9

Power Management Events (PME/SCI) .....................................................................................................32

Chapter 6

Functional Description..........................................................................................................33

6.1

Super I/O Registers....................................................................................................................................33

6.2

Host Processor Interface (LPC) .................................................................................................................34

6.3

LPC Interface .............................................................................................................................................34

6.3.1

LPC Interface Signal Definition ...........................................................................................................34

6.3.2

LPC Cycles .........................................................................................................................................34

6.3.3

Field Definitions...................................................................................................................................34

6.3.4

NLFRAME Usage................................................................................................................................35

6.3.5

I/O Read and Write Cycles..................................................................................................................35

6.3.6

DMA Read and Write Cycles ..............................................................................................................35

6.3.7

DMA Protocol ......................................................................................................................................35

6.3.8

Power Management ............................................................................................................................36

6.3.9

SYNC Protocol ....................................................................................................................................36

6.3.10

I/O and DMA START Fields.............................................................................................................37

6.3.11

LPC Transfers .................................................................................................................................37

6.4

Floppy Disk Controller ................................................................................................................................38

6.4.1

FDC Configuration Registers ..............................................................................................................38

6.4.2

FDC Internal Registers........................................................................................................................38

6.4.3

Status Register A (SRA) .....................................................................................................................39

6.4.4

Status Register B (SRB) .....................................................................................................................40

6.4.5

Digital Output Register (DOR).............................................................................................................42

6.4.6

Tape Drive Register (TDR) .................................................................................................................43

6.4.7

Data Rate Select Register (DSR)........................................................................................................44

6.4.8

Main Status Register...........................................................................................................................46

6.4.9

Data Register (FIFO)...........................................................................................................................47

6.4.10

Digital Input Register (DIR)..............................................................................................................48

6.4.11

Configuration Control Register (CCR) .............................................................................................49

6.4.12

Status Register Encoding ................................................................................................................50

6.5

Modes of Operation....................................................................................................................................52

6.5.1

PC/AT Mode .......................................................................................................................................52

6.5.2

PS/2 Mode ..........................................................................................................................................52

6.5.3

Model 30 Mode ...................................................................................................................................52

6.6

DMA Transfers ...........................................................................................................................................52

6.7

Controller Phases.......................................................................................................................................53

6.7.1

Command Phase ................................................................................................................................53

6.7.2

Execution Phase .................................................................................................................................53

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