LINR2 datasheet(91/108 Pages) FUJITSU

91 / 108 page

MB96320 Series

FME-MB96320 rev 7

Accuracy and setting of the A/D Converter sampling time

If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal

sample and hold capacitor is insufﬁcient, adversely affecting the A/D conversion precision.

To satisfy the A/D conversion precision, a sufﬁcient sampling time must be selected. The required sampling time

depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and

the AVcc voltage level. The following replacement model can be used for the calculation:

The sampling time should be set to minimum “7

τ“. The following approximation formula for the replacement

model above can be used:

Tsamp [min] = 7

× (Rext × (Cext + CIN) + (Rext + RADC) × CADC)

• Do not select a sampling time below the absolute minimum permitted value

(0.5

µs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 µs for 3.0V ≤ AVcc < 4.5V).

• If the sampling time cannot be sufﬁcient, connect a capacitor of about 0.1

µF to the analog input pin. In this

case the internal sampling capacitance CADC will be charged out of this external capacitance.

• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input

leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total

leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL

cannot be compensated by an external capacitor.

• The accuracy gets worse as |AVRH - AVRL| becomes smaller.

Comparator

Sampling switch

RADC

CADC

Analog

Rext

Cext

input

MCU

Source

Rext: external driving impedance

Cext: capacitance of PCB at A/D converter input

RADC: resistance within MCU: 2.6k

Ω (max) for 4.5V ≤ AVcc ≤ 5.5V

12k

Ω (max) for 3.0V ≤ AVcc < 4.5V

CADC: sampling capacitance within MCU: 10pF (max)

CIN

CIN: capacitance of MCU input pin: 15pF (max)

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