LINR2 datasheet(87/108 Pages) FUJITSU

87 / 108 page

MB96320 Series

FME-MB96320 rev 7

I2C Timing

*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.

*2 : Cb = capacitance of one bus line in pF.

*3 : tCLKP1 is the cycle time of the periperal clock CLKP1.

•VOH = 0.7 * VCC

•VOL = 0.3 * VCC

• CMOS Hysteresis 0.7/0.3 input selected

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V)

Parameter

Symbol

Standard-mode

Fast-mode*1

Unit

Min

Max

Min

Max

SCL clock frequency

fSCL

100

400

kHz

Hold time (repeated) START condition

SDA

↓→SCL↓

tHDSTA

4.0

⎯

0.6

⎯µs

“L” width of the SCL clock

tLOW

4.7

⎯

1.3

⎯µs

“H” width of the SCL clock

tHIGH

4.0

⎯

0.6

⎯µs

Set-up time for a repeated START condition

SCL

↑→SDA↓

tSUSTA

4.7

⎯

0.6

⎯µs

Data hold time

SCL

↓→SDA↓↑

tHDDAT

3.45

0.9

µs

Data set-up time

SDA

↓↑→SCL↑

tSUDAT

250

⎯

100

⎯

Set-up time for STOP condition

SCL

↑→SDA↑

tSUSTO

4.0

⎯

0.6

⎯µs

Bus free time between a STOP and START

condition

tBUS

4.7

⎯

1.3

⎯µs

Output fall time from 0.7*Vcc to 0.3*Vcc with

a bus capacitance from 10 pF to 400 pF

tof

20 + 0.1*Cb *2

250

20 + 0.1*Cb *2

250

Capacitive load for each bus line

⎯

400

⎯

400

Pulse width of spikes which will be sup-

pressed by input noise filter

tSP

n/a

1*tCLKP1*3

SDA

SCL

tLOW

tSUDAT

tHDSTA

tBUS

tHDSTA

tHDDAT

tHIGH

tSUSTA

tSUSTO

LINR2 bảng dữ liệu(PDF) 87 Page - fujitsu semiconductor

LINR2 bảng dữ liệu(HTML) 87 Page - fujitsu semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL