LINR2 datasheet(77/108 Pages) FUJITSU

77 / 108 page

MB96320 Series

FME-MB96320 rev 7

Bus Timing (Read)

(TA

=−40 °Cto +125 °C, VCC = 5.0 V ± 10%,VSS = 0.0 V, IOdrive =5mA,CL = 50pF)

Parameter

Sym-

bol

Conditions

Value

Unit

Remarks

Min

Max

ALE pulse width

tLHLL ALE

EACL:STS=0 and

EACL:ACE=0

tCYC/2

− 5

⎯

EACL:STS=1

tCYC

− 5

⎯

EACL:STS=0 and

EACL:ACE=1

3tCYC/2

− 5

⎯

Valid address

⇒ ALE ↓ time

tAVLL ALE, A[23:16],

EACL:STS=0 and

EACL:ACE=0

tCYC

− 15

⎯

EACL:STS=1 and

EACL:ACE=0

3tCYC/2

− 15

⎯

EACL:STS=0 and

EACL:ACE=1

2tCYC

− 15

⎯

EACL:STS=1 and

EACL:ACE=1

5tCYC/2

− 15

⎯

tADVLL ALE,AD[15:0]

EACL:STS=0 and

EACL:ACE=0

tCYC/2

− 15

⎯

EACL:STS=1 and

EACL:ACE=0

tCYC

− 15

⎯

EACL:STS=0 and

EACL:ACE=1

3tCYC/2

− 15

⎯

EACL:STS=1 and

EACL:ACE=1

2tCYC

− 15

⎯

ALE

↓

⇒ Address valid time

tLLAX ALE, AD[15:0]

EACL:STS=0

tCYC/2

− 15

⎯

EACL:STS=1

-15

⎯

Valid address

⇒ RDX ↓ time

tAVRL

RDX, A[23:16]

EACL:ACE=0

3tCYC/2

− 15

⎯

EACL:ACE=1

5tCYC/2

− 15

⎯

tADVRL RDX, AD[15:0]

EACL:ACE=0

tCYC

− 15

⎯

EACL:ACE=1

2tCYC

− 15

⎯

Valid address

⇒ Valid data input

tAVDV

A[23:16],

AD[15:0]

EACL:ACE=0

⎯

3tCYC

− 55

w/o cycle

extension

EACL:ACE=1

⎯

4tCYC

− 55

tADVDV AD[15:0]

EACL:ACE=0

⎯

5tCYC/2

− 55

w/o cycle

extension

EACL:ACE=1

⎯

7tCYC/2

− 55

RDX pulse width

tRLRH RDX

⎯

3 tCYC/2

− 5

⎯

w/o cycle

extension

RDX

↓⇒ Valid data input tRLDV RDX, AD[15:0]

⎯⎯

3tCYC/2

− 50 ns

w/o cycle

extension

RDX

↑⇒ Data hold time

tRHDX RDX, AD[15:0]

⎯

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