LINR2 datasheet(8/108 Pages) FUJITSU

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MB96320 Series

FME-MB96320 rev 7

■ BLOCK DIAGRAM

Block diagram of MB96(F)32x

16FX

CPU

DMA

Controller

Interrupt

Controller

Boot ROM

Peripheral

Bus Bridge

Clock &

Mode Controller

Flash

Peripheral

Bus Bridge

16FX Core Bus (CLKB)

USART

4 ch.

I2C

1 ch.

10-bit ADC

18 ch.

16-bit Reload

Timer

4 ch.

I/O Timer 0

ICU 0/1/2/3

I/O Timer 1

ICU 4/5/6/7

OCU 4/5/6/7

I/O Timer 2

ICU 8/9

I/O Timer 3

ICU 10/11

16-bit PPG

20 ch.

CAN

Interface

2 ch.

External

Interrupt

Real Time

Clock

Memory Patch

Unit

Watchdog

RAM

Voltage

Regulator

SIN2, SIN2_R, SIN3, SIN7_R, SIN8_R

SOT2, SOT2_R, SOT3, SOT7_R, SOT8_R

SCK2, SCK2_R, SCK3, SCK7_R, SCK8_R

WOT

SDA0

SCL0

AVCC

AVSS

AVRH

AN0 ... AN17

ADTG_R

TIN0_R, TIN2_R

FRCK0

IN0 ... IN3

FRCK1

IN4 ... IN7

OUT4 ... OUT7

FRCK2_R

IN8, IN9

FRCK3

IN10,IN11

INT0, INT1, INT8 ... INT15

TX1, TX2 *2

RX1, RX2 *2

AD00 ... AD15

A16 ... A23

ALE

RDX

WR(L)X, WRHX

HRQ

HAKX

RDY

ECLK

External Bus

Interface

VCC

VSS

PPG0 ... PPG15, PPG17 ... PPG19

TTG0 ... TTG15, TTG17 ... TTG19

LBX, UBX

CS0_R ... CS5_R, CS4, CS5

NMI, NMI_R

OUT10_R, OUT11

OCU 10/11

INT0_R, INT2_R ... INT5_R

INT3_R1

INT7_R, INT9_R ... INT11_R

PPG8_R ... PPG11_R, PPG16_R ... PPG19_R

TTG8_R ... TTG11_R, TTG16_R ... TTG19_R

TIN1, TIN3

TOT0_R, TOT2_R

TOT1, TOT3

Memory A

CKOT0_R, CKOT1, CKOT1_R

CKOTX1

X0, X1

X0A, X1A *1

RSTX

MD0...MD2

*1: X0A, X1A only available on devices with sufﬁx “W”

RLT6

*2: CAN interfaces are not available on MB96F326A

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