LAN9115 datasheet(98/114 Pages) MICROCHIP

98 / 114 page

LAN9115

DS00002269A-page 98

 2005-2016 Microchip Technology Inc.

6.3

PIO Burst Reads

In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO Burst Reads can be

performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between

bursts for the period specified.

6.4

RX Data FIFO Direct PIO Reads

In this mode the upper address inputs are not decoded, and any read of the LAN9115 will read the RX Data FIFO. This

mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the

FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address

when accessing the LAN9115. Timing is identical to a PIO read, and the FIFO_SEL signal has the same timing charac-

teristics as the address lines.

Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.

FIGURE 6-2:

LAN9115 PIO BURST READ CYCLE TIMING

Note:

The “Data Bus” width is 16 bits.

TABLE 6-4:

PIO BURST READ TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tacyc

Address Cycle Time

165

tasu

Address Setup to nCS, nRD valid

tadv

Address Stable to Data Valid

tah

Address Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Note:

A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both

nCS and nRD are deasserted. They may be asserted and deasserted in any order.

Data Bus

nCS, nRD

A[7:5]

A[4:1]

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