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LAN9115 bảng dữ liệu(PDF) 49 Page - Microchip Technology

tên linh kiện LAN9115
Giải thích chi tiết về linh kiện  Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
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LAN9115 bảng dữ liệu(HTML) 49 Page - Microchip Technology

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 2005-2016 Microchip Technology Inc.
DS00002269A-page 49
LAN9115
Note 3-1
The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits
wide. Figure 3-19 describes the host read ordering for pairs of atomic 16-bit transactions.
3.14.3
RX STATUS FORMAT
FIGURE 3-19:
RX PACKET FORMAT
Bits
Description
31
Reserved. This bit is reserved. Reads 0.
30
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
filtering.
29:16
Packet Length. The size, in bytes, of the corresponding received frame.
15
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the Internal
logical “or” of bits 11,7,6 and 1.
14
Reserved. These bits are reserved. Reads 0.
13
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
12
Length Error (LE). When set, this bit indicates that the actual length does not match with the
length/type field of the received frame.
11
Runt Frame. When set, this bit indicates that frame was prematurely terminated before the collision
window (64 bytes). Runt frames are passed on to the host only if the Pass Bad Frames bit MAC_CR
Bit [16] is set.
10
Multicast Frame. When set, this bit indicates that the received frame has a Multicast address.
ofs + First Data DWORD
.
.
.
.
Last Data DWORD
0
31
Host Read
Order
1st
2nd
Last
Optional Pad DWORD0
.
.
Optional Pad DWORDn
Optional offset DWORD0
.
.
Optional offset DWORDn



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