LAN9115 datasheet(84/114 Pages) MICROCHIP

84 / 114 page

LAN9115

DS00002269A-page 84

 2005-2016 Microchip Technology Inc.

5.4.5

HASHL—MULTICAST HASH TABLE LOW REGISTER

This register defines the lower 32-bits of the Multicast Hash Table. Please refer to Table 5.4.4, "HASHH—Multicast Hash

Table High Register" for further details.

5.4.6

MII_ACC—MII ACCESS REGISTER

This register is used to control the Management cycles to the PHY.

Offset:

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

Bits

Description

31-0

Lower 32 bits of the 64-bit Hash Table

Offset:

Attribute:

R/W

Default Value:

00000000h

Size:

32 bits

Bits

Description

31-16

Reserved

15-11

PHY Address: Selects the external or internal PHY based on its address. The internal PHY is set to

address 00001b.

10-6

MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.

5-2

Reserved

MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data

MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete.

This bit must read a logical 0 before writing to this register and MII data register.

The LAN driver software must set (1) this bit in order for the LAN9115 to read or write any of the MII

PHY registers.

During a MII register access, this bit will be set, signifying a read or write access is in progress. The

MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The

MII data register is invalid until the MAC has cleared this bit during a PHY read operation.

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