MT9072AB datasheet(208/275 Pages) ZARLINK

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MT9072

Data Sheet

208

Zarlink Semiconductor Inc.

8CEIM

(0)

CRC-4 Error Counter Indication Mask. This is the mask bit for the CEII interrupt status bit in

the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address

Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

VEOM

(0)

Bipolar Violation (BPV) Error Counter Overflow Mask. This is the mask bit for the VEOI

interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt Status

inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.

VEIM

(0)

Bipolar Violation (BPV) Error Counter Indication Mask. This is the mask bit for the VEII

interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt Status

inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.

EEOM

(0)

E-Bit Error Counter Overflow Mask. This is the mask bit for the EEOI interrupt status bit in

the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address

Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

EEIM

(0)

E-Bit Error Counter Indication Mask. This is the mask bit for the EEII interrupt status bit in

the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address

Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

3PCOM

(0)

PRBS CRC-4 Counter Overflow Mask. This is the mask bit for the PCOI interrupt status bit

in the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address

Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

(0)

not used.

PEOM

(0)

PRBS Error Counter Overflow Mask. This is the mask bit for the PEOI interrupt status bit in

the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address

Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

PEIM

(0)

PRBS Error Counter Indication Mask. This is the mask bit for the PEII interrupt status bit in

the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address

Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit

is zero, the corresponding interrupt bit will function normally.

Bit

Name

Functional Description

Table 183 - Counter (Counter Indication and Counter Overflow) Interrupt Mask Register (Address Y45)

(E1)

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