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TMS320C6711 bảng dữ liệu(PDF) 100 Page - Texas Instruments |
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TMS320C6711 bảng dữ liệu(HTML) 100 Page - Texas Instruments |
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100 / 129 page ![]() TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HOST-PORT INTERFACE TIMING (CONTINUED) switching characteristics over recommended operating conditions during host-port interface cycles†‡ (see Figure 46, Figure 47, Figure 48, and Figure 49) [C6711C/C6711D] NO. PARAMETER 11CGDPA-167 11C−200 11DGDPA-167 11D−200 11D−250 UNIT MIN MAX MIN MAX 5 td(HCS-HRDY) Delay time, HCS to HRDY§ 1 15 1 12 ns 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 3 15 3 12 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 2 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P − 4 2P − 4 ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 12 3 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 2 12 3 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 10P + 5.8 3 12.5 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 15 3 12 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. § HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. ¶ Make sure the external host meets the timing specifications of the C6711C device. Delays or buffers may be needed to compensate for any timing differences. IBIS analysis should be used to correctly model the system interface. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. |
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