TMS320C6711 datasheet(79/129 Pages) TI

79 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS-BURST MEMORY TIMING

timing requirements for synchronous-burst SRAM cycles† (see Figure 32) [C6711]

C6711-100

C6711-150

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-EKOH)

Setup time, read EDx valid before ECLKOUT high

2.5

th(EKOH-EDV)

Hold time, read EDx valid after ECLKOUT high

2.1‡

timing requirements for synchronous-burst SRAM cycles† (see Figure 32) [C6711B]

NO.

C6711B-100

C6711BGFNA-100

C6711B-150

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-EKOH)

Setup time, read EDx valid before ECLKOUT high

2.5

th(EKOH-EDV)

Hold time, read EDx valid after ECLKOUT high

2.5

timing requirements for synchronous-burst SRAM cycles† (see Figure 32) [C6711C/C6711D]

NO.

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

tsu(EDV-EKOH)

Setup time, read EDx valid before ECLKOUT high

1.5

th(EKOH-EDV)

Hold time, read EDx valid after ECLKOUT high

2.5

† The C6711/11B/11C/11D SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing

4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous

data flow.

‡ Make sure the external SBSRAM meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any

timing differences. IBIS analysis should be used to correctly model the system interface.

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