TMS320C6711 datasheet(69/129 Pages) TI

69 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

Vref = 1.5 V

Figure 20. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and

VOL MAX and VOH MIN for output clocks.

Vref = VIL MAX (or VOL MAX)

Vref = VIH MIN (or VOH MIN)

Figure 21. Rise and Fall Transition Time Voltage Reference Levels

timing parameters and board routing analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good

board design practice, such delays must always be taken into account. Timing values may be adjusted by

increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification

(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate

timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature

number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing

differences.

For example:

D In typical boards with the C6711B commercial temperature device, the routing delay improves the external

memory’s ability to meet the DSP’s EMIF data input hold time requirement [th(EKOH-EDV)].

D In some boards with the C6711BGFNA extended temperature device, the routing delay improves the

external memory’s ability to meet the DSP’s EMIF data input hold time requirement [th(EKOH-EDV)]. In

addition, it may be necessary to add an extra delay to the input clock of the external memory to robustly

meet the DSP’s data input hold time requirement. If the extra delay approach is used, memory bus

frequency adjustments may be needed to ensure the DSP’s input setup time requirement [tsu(EDV-EKOH)]

is still maintained.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and

from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,

but also tends to improve the input hold time margins (see Table 40 and Figure 22).

Figure 22 represents a general transfer between the DSP and an external device. The figure also represents

board route delays and how they are perceived by the DSP and the external device.

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