TMS320C6711 datasheet(85/129 Pages) TI

85 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS DRAM TIMING (CONTINUED)

switching characteristics over recommended operating conditions for synchronous DRAM

cycles†‡ (see Figure 34−Figure 40) [C6711C/C6711D]

NO.

PARAMETER

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

td(EKOH-CEV)

Delay time, ECLKOUT high to CEx valid

1.5

td(EKOH-BEV)

Delay time, ECLKOUT high to BEx valid

td(EKOH-BEIV)

Delay time, ECLKOUT high to BEx invalid

1.5

td(EKOH-EAV)

Delay time, ECLKOUT high to EAx valid

td(EKOH-EAIV)

Delay time, ECLKOUT high to EAx invalid

1.5

td(EKOH-CASV)

Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid

1.5

td(EKOH-EDV)

Delay time, ECLKOUT high to EDx valid

td(EKOH-EDIV)

Delay time, ECLKOUT high to EDx invalid

1.5

td(EKOH-WEV)

Delay time, ECLKOUT high to AWE/SDWE/SSWE valid

1.5

td(EKOH-RAS)

Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid

1.5

† The C6711/11B/11C/11D SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word

bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

‡ ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

ECLKOUT

CEx

BE[3:0]

EA[11:2]

ED[31:0]

EA12

AOE/SDRAS/SSOE†

ARE/SDCAS/SSADS†

AWE/SDWE/SSWE†

EA[21:13]

BE1

BE2

BE3

BE4

Bank

Column

READ

† ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 34. SDRAM Read Command (CAS Latency 3)

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