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TMS320C6711 bảng dữ liệu(PDF) 97 Page - Texas Instruments |
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TMS320C6711 bảng dữ liệu(HTML) 97 Page - Texas Instruments |
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97 / 129 page  TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 97 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 46, Figure 47, Figure 48, and Figure 49) [C6711] NO. C6711-100 C6711-150 UNIT NO. MIN MAX UNIT 1 tsu(SELV-HSTBL) Setup time, select signals¶ valid before HSTROBE low 5 ns 2 th(HSTBL-SELV) Hold time, select signals¶ valid after HSTROBE low 6§ ns 3 tw(HSTBL) Pulse duration, HSTROBE low 4P ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P ns 10 tsu(SELV-HASL) Setup time, select signals¶ valid before HAS low 5 ns 11 th(HASL-SELV) Hold time, select signals¶ valid after HAS low 3 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 6§ ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 4§ ns timing requirements for host-port interface cycles†‡ (see Figure 46, Figure 47, Figure 48, and Figure 49) [C6711B] NO. C6711B-100 C6711B-150 C6711BGFNA-100 UNIT NO. MIN MAX MIN MAX UNIT 1 tsu(SELV-HSTBL) Setup time, select signals¶ valid before HSTROBE low 5 5 ns 2 th(HSTBL-SELV) Hold time, select signals¶ valid after HSTROBE low 4 4 ns 3 tw(HSTBL) Pulse duration, HSTROBE low 4P 4P ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P 4P ns 10 tsu(SELV-HASL) Setup time, select signals¶ valid before HAS low 5 5 ns 11 th(HASL-SELV) Hold time, select signals¶ valid after HAS low 3 3 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 5 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3 3 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 2 ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 2 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. § Make sure the external host meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any timing differences. IBIS analysis should be used to correctly model the system interface. ¶ Select signals include: HCNTL[1:0], HR/W, and HHWIL. |
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