TMS320DM355 datasheet(94/163 Pages) TI1

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TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

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3.13 Power Management

The DM355 is designed for minimal power consumption. There are two components to power

consumption: active power and leakage power. Active power is the power consumed to perform work and

scales with clock frequency and the amount of computations being performed. Active power can be

reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to

complete the required operation in the required timeline or to run at a clock setting until the work is

complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be

performed. Leakage power is due to static current leakage and occurs regardless of the clock rate.

Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating

junction temperatures. Leakage power can only be avoided by removing power completely from a device

or subsystem. The DM355 includes several power management features which are briefly described in

Table 3-17. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference

Guide (literature number SPRUFB3) for more information on power management.

Table 3-27. Power Management Features

Power Management Features

Description

Clock Management

Module clock disable

Module clocks can be disabled to reduce switching power

Module clock frequency scaling

Module clock frequency can be scaled to reduce switching power

PLL power-down

The PLLs can be powered-down when not in use to reduce

switching power

ARM Sleep Mode

ARM Wait-for-Interrupt sleep mode

Disable ARM clock to reduce active power

System Sleep Modes

Deep Sleep mode

Stop all device clocks and power down internal oscillators to reduce

active power to a minimum. Registers and memory are preserved.

I/O Management

USB Phy power-down

The USB Phy can be powered-down to reduce USB I/O power

DAC power-down

The DAC's can be powered-down to reduce DAC power

DDR self-refresh and power down

The DDR / mDDR device can be put into self-refresh and power

down states

Detailed Device Description

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