TMS320DM355 datasheet(65/163 Pages) TI1

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TMS320DM355

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SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

3.3.2

External Memories

The ARM has access to the following External memories:

•

DDR2 / mDDR Synchronous DRAM

•

Asynchronous EMIF / OneNAND

•

NAND Flash

•

Flash card devices:

–

MMC/SD

–

SmartMedia

3.3.3

Peripherals

The ARM has access to all of the peripherals on the DM355 device.

3.4

ARM Interrupt Controller (AINTC)

The DM355 ARM Interrupt Controller (AINTC) has the following features:

•

Supports up to 64 interrupt channels (16 external channels)

•

Interrupt mask for each channel

•

Each interrupt channel can be mapped to a Fast Interrupt Request (FIQ) or to an Interrupt Request

(IRQ) type of interrupt.

•

Hardware prioritization of simultaneous interrupts

•

Configurable interrupt priority (2 levels of FIQ and 6 levels of IRQ)

•

Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time

The ARM core supports two interrupt types: FIQ and IRQ. See the ARM926EJ-S Technical Reference

Manual for detailed information about the ARM’s FIQ and IRQ interrupts. Each interrupt channel is

mappable to an FIQ or to an IRQ type of interrupt, and each channel can be enabled or disabled. The

INTC supports user-configurable interrupt-priority and interrupt entry addresses. Entry addresses minimize

the time spent jumping to interrupt service routines (ISRs). When an interrupt occurs, the corresponding

highest priority ISR’s address is stored in the INTC’s ENTRY register. The IRQ or FIQ interrupt routine can

read the ENTRY register and jump to the corresponding ISR directly. Thus, the ARM does not require a

software dispatcher to determine the asserted interrupt.

3.4.1

Interrupt Mapping

The AINTC takes up to 64 ARM device interrupts and maps them to either the IRQ or to the FIQ of the

ARM. Each interrupt is also assigned one of 8 priority levels (2 for FIQ, 6 for IRQ). For interrupts with the

same priority level, the priority is determined by the hardware interrupt number (the lowest number has the

highest priority). Table 3-1 shows the connection of device interrupts to the ARM.

Table 3-1. AINTC Interrupt Connections(1)

Interrupt

Acronym

Source

Interrupt

Acronym

Source

Number

VPSSINT0

VPSS - INT0,

TINT0

Timer 0 - TINT12

Configurable via

VPSSBL register:

INTSEL

VPSSINT1

VPSS - INT1

TINT1

Timer 0 - TINT34

VPSSINT2

VPSS - INT2

TINT2

Timer 1 - TINT12

(1)

The total number of interrupts in DM355 exceeds 64, which is the maximum value of the AINTC module. Therefore, several interrupts

are multiplexed and you must use the register ARM_INTMUX in the System Control Module to select the interrupt source for multiplexed

interrupts. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number

SPRUFB3) for more information on the System Control Module register ARM_INTMUX.

Detailed Device Description

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