TMS320DM355 datasheet(45/163 Pages) TI1

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TMS320DM355

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SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

Table 2-23. DM355 Pin Descriptions (continued)

Name

BGA

Type Group

Power

Reset

Description(4)

Mux Control

(1)

Supply(2)

PD(3)

State

DDR_VREF

U10

PWR DDRI

VDD_DDR

DDR: Voltage input for the SSTL_18 IO

buffers

VSSA_DLL

R11

GND DDRD

VSSA_DLL

DDR: Ground for the DDR DLL

VDDA33_DDRDLL

R10

PWR DDRD

VDDA33_DDR

DDR: Power (3.3 Volts) for the DDR DLL

DLL

DDR_ZN

I/O

DDRI

VDD_DDR

DDR: Reference output for drive strength

calibration of N and P channel outputs. Tie

to ground via 50 ohm resistor @ 0.5%

tolerance.

EM_A13 /

V19

I/O

AEMI

VDD

in L

Async EMIF: Address Bus bit[13]

PINMUX2[0].EM_A1

GIO067 /

F /

3_3,

BTSEL[1]

GIO /

syste

GIO: GIO[067]

default set by

AECFG[0]

System: BTSEL[1:0] sampled at

Power-on-Reset to determine Boot method

(00:NAND, 01:Flash, 10:MMC/SD, 11:UART

)

EM_A12 /

U19

I/O

AEMI

VDD

in L

Async EMIF: Address Bus bit[12]

PINMUX2[0].EM_A1

GIO066 /

F /

3_3,

BTSEL[0]

GIO /

syste

GIO: GIO[066]

default set by

AECFG[0]

System: BTSEL[1:0] sampled at

Power-on-Reset to determine Boot method

(00:NAND, 01:Flash, 10:MMC/SD, 11:UART)

EM_A11 /

R16

I/O

AEMI

VDD

in H

Async EMIF: Address Bus bit[11]

PINMUX2[0].EM_A1

GIO065 /

F /

3_3,

AECFG[3]

GIO /

syste

GIO: GIO[065]

default set by

AECFG[0]

System: AECFG[3:0] sampled at

Power-on-Reset to set AEMIF Configuration

AECFG[3] sets default for

PinMux2.EM_D15_8: AEMIF Default Bus

Width (0:16 or 1:8 bits)

EM_A10 /

R18

I/O

AEMI

VDD

in H

Async EMIF: Address Bus bit[10]

PINMUX2[0].EM_A1

GIO064 /

F /

3_3,

AECFG[2]

GIO /

syste

GIO: GIO[064]

default set by

AECFG[0]

System: AECFG[3:0] sampled at

Power-on-Reset to set AEMIF Configuration

AECFG[2:1] sets default for

PinMux2.EM_BA0: AEMIF EM_BA0

Definition (00: EM_BA0, 01: EM_A14,

10:GIO[054], 11:rsvd)

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