CP3SP33SMSSLASHNOPB datasheet(336/407 Pages) TI1

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TIOn_y (PxPOL = 0)

DTYCAPx_n

TxRUN = 1

COUNTx_n

TIOn_y (PxPOL = 1)

PERCAPx_n

DS354

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Figure 33-2. VTU PWM Generation

The period time is determined by the following formula:

PWM Period = (PERCAPx_n + 1) × (CxPRSC + 1) × TCLK

The duty cycle in percent is calculated as follows:

Duty Cycle = (DTYCAPx_n / (PERCAPx_n + 1)) × 100

If the duty cycle register (DTYCAPx_n) holds a value which is greater than the value held in the period

corresponds to a duty cycle of 100%. If the duty cycle register (DTYCAPx_n) register holds a value of 00h,

the TIOn_y output will remain at the default value which corresponds to a duty cycle of 0%, in which case

the value in the PERCAPx_n register is irrelevant. This scheme allows the duty cycle to be programmed in

a range from 0% to 100%.

In order to allow fully synchronized updates of the period and duty cycle compare values, the PERCAPx_n

and DTYCAPx_n registers are double buffered when operating in PWM mode. Therefore, if software

writes to either the period or duty cycle register while either of the two PWM channels is enabled, the new

value will not take effect until the counter value matches the previous period value or the timer is stopped.

Reading the PERCAPx_n or DTYCAPx_n register will always return the most recent value written to it.

The counter registers can be written if both 8-bit counters are stopped. This allows software to preset the

counters before starting, which can be used to generate PWM output waveforms with a phase shift

relative to each other. If the counter is written with a value other than 00h, it will start incrementing from

that value. The TIOn_y output will remain at its default value until the first 00h to 01h transition of the

counter value occurs. If the counter is preset to values which are less than or equal to the value held in

the period register (PERCAPx_n) the counter will count up until a match between the counter value and

the PERCAPx_n register value occurs. The counter will then be cleared and continue counting up.

Alternatively, the counter may be written with a value which is greater than the value held in the period

always changes its state at the 00h to 01h transition of the counter.

Software may only write to the COUNTx_n register if both TxRUN bits of a timer subsystem are clear. Any

writes to the counter register while either timer is running will be ignored.

336

Dual Versatile Timer Units (VTU)

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