COP8CCR9IMT7SLASHNOPB datasheet(90/111 Pages) TI1

90 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

www.ti.com

Address

Contents(1)

S/ADD REG

xxFE

B Register

xxFF

S Register

0100 to 017F

On-Chip 128 RAM Bytes

0200 to 027F

On-Chip 128 RAM Bytes

0300 to 037F

On-Chip 128 RAM Bytes

0400 to 0047F

On-Chip 128 RAM Bytes

0500 to 057F

On-Chip 128 RAM Bytes

0600 to 067F

On-Chip 128 RAM Bytes

0700 to 077F

On-Chip 128 RAM Bytes

5.19 Instruction Set

5.19.1 INTRODUCTION

This section defines the instruction set of the COP8 Family members. It contains information about the

instruction set features, addressing modes and types.

5.19.2 INSTRUCTION FEATURES

The strength of the instruction set is based on the following features:

•

Mostly single-byte opcode instructions minimize program size.

•

One instruction cycle for the majority of single-byte instructions to minimize program execution time.

•

Many single-byte, multiple function instructions such as DRSZ.

•

Three memory mapped pointers: two for register indirect addressing, and one for the software stack.

•

Sixteen memory mapped registers that allow an optimized implementation of certain instructions.

•

Ability to set, reset, and test any individual bit in data memory address space, including the memory-

mapped I/O ports and registers.

•

decrementing of the register pointer. This allows for greater efficiency (both in cycle time and program

code) in loading, walking across and processing fields in data memory.

•

Unique instructions to optimize program size and throughput efficiency. Some of these instructions are:

DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.

5.19.3 ADDRESSING MODES

The instruction set offers a variety of methods for specifying memory addresses. Each method is called an

addressing mode. These modes are classified into two categories: operand addressing modes and

transfer-of-control addressing modes. Operand addressing modes are the various methods of specifying

an address for accessing (reading or writing) data. Transfer-of-control addressing modes are used in

conjunction with jump instructions to control the execution sequence of the software program.

5.19.3.1 Operand Addressing Modes

The operand of an instruction specifies what memory location is to be affected by that instruction. Several

different operand addressing modes are available, allowing memory locations to be specified in a variety

of ways. An instruction can specify an address directly by supplying the specific address, or indirectly by

specifying a register pointer. The contents of the register (or in some cases, two registers) point to the

desired memory location. In the immediate mode, the data byte to be used is contained in the instruction

itself.

Each addressing mode has its own advantages and disadvantages with respect to flexibility, execution

speed, and program compactness. Not all modes are available with all instructions. The Load (LD)

instruction offers the largest number of addressing modes.

Functional Description

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Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

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