COP8CCR9IMT7SLASHNOPB datasheet(27/111 Pages) TI1

27 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

SP (Stack Pointer):

Initialized to RAM address 06F Hex

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

S Register: CLEARED

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

USART:

PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit

which is set to one.

ANALOG TO DIGITAL CONVERTER:

ENAD: CLEARED

ADRSTH: RANDOM

ADRSTL: RANDOM

ISP CONTROL:

ISPADLO: CLEARED

ISPADHI: CLEARED

PGMTIM: PRESET TO VALUE FOR 10 MHz CKI

WATCHDOG (if enabled):

The device comes out of reset with both the WATCHDOG logic and the Clock Monitor

detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set.

The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG

service window bits being initialized high default to the maximum WATCHDOG service

window of 64k T0 clock cycles. The Clock Monitor bit being initialized high will cause a Clock

Monitor error following reset if the clock has not reached the minimum specified frequency at

the termination of reset. A Clock Monitor error will cause an active low error output on pin

G1. This error output will continue until 16–32 T0 clock cycles following the clock frequency

reaching the minimum specified value, at which time the G1 output will go high.

5.7.1

External Reset

The RESET input when pulled low initializes the device. The RESET pin must be held low for a minimum

of one instruction cycle to ensure a valid reset. During Power-Up initialization, the user must ensure that

the RESET pin of a device without the Brownout Reset feature is held low until the device is within the

specified VCC voltage. Any rising edge on the RESET pin while VCC is below the specified operating range

may cause unpredictable results. An R/C circuit on the RESET pin with a delay 5 times (5x) greater than

the power supply rise time is recommended. Reset should also be wide enough to ensure crystal start-up

upon Power-Up.

RESET may also be used to cause an exit from the HALT mode.

A recommended reset circuit for this device is shown in Figure 5-3.

Functional Description

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Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

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