AM1705DPTP4 datasheet(95/165 Pages) TI1

95 / 165 page

AM1705

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SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014

Table 6-47. McASP1 Switching Characteristics(1)

No.

PARAMETER

MIN

MAX

UNIT

Cycle time, AHCLKR1 internal, AHCLKR1 output

Cycle time, AHCLKR1 external, AHCLKR1 output

tc(AHCLKRX)

Cycle time, AHCLKX1 internal, AHCLKX1 output

Cycle time, AHCLKX1 external, AHCLKX1 output

Pulse duration, AHCLKR1 internal, AHCLKR1 output

(AHR/2) – 2.5(2)

Pulse duration, AHCLKR1 external, AHCLKR1 output

(AHR/2) – 2.5(2)

tw(AHCLKRX)

Pulse duration, AHCLKX1 internal, AHCLKX1 output

(AHX/2) – 2.5(3)

Pulse duration, AHCLKX1 external, AHCLKX1 output

(AHX/2) – 2.5(3)

Cycle time, ACLKR1 internal, ACLKR1 output

greater of 2P or 25 ns(4)

Cycle time, ACLKR1 external, ACLKR1 output

greater of 2P or 25 ns(4)

tc(ACLKRX)

Cycle time, ACLKX1 internal, ACLKX1 output

greater of 2P or 25 ns(4)

Cycle time, ACLKX1 external, ACLKX1 output

greater of 2P or 25 ns(4)

Pulse duration, ACLKR1 internal, ACLKR1 output

(AR/2) – 2.5(5)

Pulse duration, ACLKR1 external, ACLKR1 output

(AR/2) – 2.5(5)

tw(ACLKRX)

Pulse duration, ACLKX1 internal, ACLKX1 output

(AX/2) – 2.5(6)

Pulse duration, ACLKX1 external, ACLKX1 output

(AX/2) – 2.5(6)

Delay time, ACLKR1 internal, AFSR output(7)

0.5

6.7

Delay time, ACLKX1 internal, AFSX output

0.5

6.7

Delay time, ACLKR1 external input, AFSR output (7)

3.4

13.8

td(ACLKRX-AFSRX)

Delay time, ACLKX1 external input, AFSX output

3.4

13.8

Delay time, ACLKR1 external output, AFSR output (7)

3.4

13.8

Delay time, ACLKX1 external output, AFSX output

3.4

13.8

Delay time, ACLKX1 internal, AXR1[n] output

0.5

6.7

td(ACLKX-AXRV)

Delay time, ACLKX1 external input, AXR1[n] output

3.4

13.8

Delay time, ACLKX1 external output, AXR1[n] output

3.4

13.8

Disable time, ACLKX1 internal, AXR1[n] output

0.5

6.7

tdis(ACLKX-AXRHZ)

Disable time, ACLKX1 external input, AXR1[n] output

3.9

13.8

Disable time, ACLKX1 external output, AXR1[n] output

3.9

13.8

(1)

McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1

McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

AHR - Cycle time, AHCLKR1.

(3)

AHX - Cycle time, AHCLKX1.

(4)

P = SYSCLK2 period

(5)

AR - ACLKR1 period.

(6)

AX - ACLKX1 period.

(7)

McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1

Peripheral Information and Electrical Specifications

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